C8051F39x/37x
While in the SPI0 ISR, a PCA interrupt occurs. Recall the PCA interrupt is configured as a high priority
interrupt, while the SPI0 interrupt is configured as a low priority interrupt. Thus, the CIP-51 will now vector
to the high priority PCA ISR. Upon doing so, the value that was in the SFRPGIDX = 001b location before
the PCA interrupt (in this case SFR page 0x0F for TS0CN) is pushed down to the SFRPGIDX = 010b loca-
tion. Likewise, the value that was in the SFRPAGE register before the PCA interrupt (SFR page 0x00 for
SPI0) is pushed down the stack into the SFRPGIDX = 001b location. Lastly, the CIP-51 will automatically
places the SFR page needed to access the PCA0’s special function registers into the SFRPAGE register,
SFR page 0x00. See Figure 19.4.
SFRPGIDX[2:0]
3) SFRPAGE automatically set
to 0x00 on PCA0 interrupt
SFRPAGE = 0x00
000
(PCA0)
0x00
2) SFRPAGE is pushed to
SFRPGIDX = 001b location
001
010
011
100
(SPI0)
0x0F
(TS0CN)
1)Value at SFRPGIDX = 001b location is
pushed to SFRPGIDX = 010b location
SFRSTACK
Figure 19.4. SFR Page Stack Upon PCA Interrupt Occurring During a SPI0 ISR
Preliminary Rev. 0.71
103
SILICON [ SILICON ]
