C8051F39x/37x
19. Special Function Registers
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers
(SFRs). The SFRs provide control and data exchange with the C8051F39x/37x's resources and peripher-
als. The CIP-51 controller core duplicates the SFRs found in a typical 8051 implementation as well as
implementing additional SFRs used to configure and access the sub-systems unique to the C8051F39x/
37x. This allows the addition of new functionality while retaining compatibility with the MCS-51™ instruc-
tion set. Table 19.2 lists the SFRs implemented in the C8051F39x/37x device family.
The SFR registers are accessed anytime the direct addressing mode is used to access memory locations
from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g. P0, TCON, SCON0, IE, etc.) are bit-
addressable as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied
addresses in the SFR space are reserved for future use. Accessing these areas will have an indeterminate
effect and should be avoided. Refer to the corresponding pages of the data sheet, as indicated in
Table 19.3, for a detailed description of each register.
19.1. SFR Paging
The CIP-51 features SFR paging, allowing the device to map many SFRs into the 0x80 to 0xFF memory
address space. The SFR memory space has 256 pages. In this way, each memory location from 0x80 to
0xFF can access up to 256 SFRs. The C8051F39x/37x devices utilize two SFR pages: 0x0, and 0xF. Most
SFRs are available on both pages. SFR pages are selected using the Special Function Register Page
Selection register, SFRPAGE. The procedure for reading and writing an SFR is as follows:
1. Select the appropriate SFR page number using the SFRPAGE register.
2. Use direct accessing mode to read or write the special function register (MOV instruction).
19.2. Interrupts and Automatic SFR Paging
When an interrupt occurs, the current SFRPAGE is pushed onto the SFR page stack. Upon execution of
the RETI instruction, the SFR page is automatically restored to the SFR page in use prior to the interrupt.
This is accomplished via a five-byte SFR page stack, depicted in Figure 19.1. Firmware can read any ele-
ment of the SFR page stack by setting the SFR Page Stack Index (SFRPGIDX) in the SFR Page Control
Register (SFRPGCN) and reading the SFRSTACK register:
Table 19.1. SFR Page Stack
SFRPGIDX Value
SFRSTACK Contains
000b
001b
011b
010b
100b
Value of the first/top* byte of the stack
Value of the second byte of the stack
Value of the third byte of the stack
Value of the forth byte of the stack
Value of the fifth/bottom byte of the stack
*Note: The first/top byte of the stack can also be directly accessed by reading SFRPAGE.
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