C8051F360/1/2/3/4/5/6/7/8/9
12.1. Power-On Reset
During power-up, the device is held in a reset state and the RST pin is driven low until V settles above
DD
V
. A delay occurs before the device is released from reset; the delay decreases as the V ramp time
RST
DD
increases (V
ramp time is defined as how fast V
ramps from 0 V to V ). Figure 12.2. plots the
RST
DD
DD
power-on and V Monitor reset timing. For ramp times less than 1 ms, the power-on reset delay (T
DD
PORDe-
) is typically less than 0.3 ms.
lay
Note: The maximum V ramp time is 1 ms; slower ramp times may cause the device to be released from
DD
reset before V reaches the V
level.
DD
RST
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic ‘1’. When PORSF
is set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other
resets). Since all resets cause program execution to begin at the same location (0x0000) software can
read the PORSF flag to determine if a power-up was the cause of reset. The content of internal data mem-
ory should be assumed to be undefined after a power-on reset. The V
power-on reset.
Monitor is enabled following a
DD
VDD
2.70
2.55
VRST
2.0
1.0
t
/RST
Logic HIGH
TPORDelay
Logic LOW
VDD
Power-On
Reset
Monitor
Reset
Figure 12.2. Power-On and V Monitor Reset Timing
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Rev. 1.0
129
SILICON [ SILICON ]
