C8051F360/1/2/3/4/5/6/7/8/9
SFR Definition 12.2. RSTSRC: Reset Source
SFR Page:
all pages
SFR Address: 0xEF
R
R
R/W
R/W
R
R/W
R/W
R
Reset Value
–
Bit7
FERROR C0RSEF SWRSF WDTRSF MCDRSF PORSF
PINRSF
Bit0
Variable
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Note:For bits that act as both reset source enables (on a write) and reset indicator flags (on a read),
read-modify-write instructions read and modify the source enable only. [This applies to bits:
C0RSEF, SWRSF, MCDRSF, PORSF].
Bit 7:
Bit 6:
UNUSED. Read = 0b. Write = don’t care.
FERROR: Flash Error Indicator.
0: Source of last reset was not a Flash read/write/erase error.
1: Source of last reset was a Flash read/write/erase error.
C0RSEF: Comparator0 Reset Enable and Flag.
Bit 5:
0: Read: Source of last reset was not Comparator0. Write: Comparator0 is not a reset
source.
1: Read: Source of last reset was Comparator0. Write: Comparator0 is a reset source
(active-low).
Bit 4:
Bit 3:
Bit 2:
SWRSF: Software Reset Force and Flag.
0: Read: Source of last reset was not a write to the SWRSF bit. Write: No Effect.
1: Read: Source of last reset was a write to the SWRSF bit. Write: Forces a system reset.
WDTRSF: Watchdog Timer Reset Flag.
0: Source of last reset was not a WDT timeout.
1: Source of last reset was a WDT timeout.
MCDRSF: Missing Clock Detector Flag.
0: Read: Source of last reset was not a Missing Clock Detector timeout. Write: Missing
Clock Detector disabled.
1: Read: Source of last reset was a Missing Clock Detector timeout. Write: Missing Clock
Detector enabled; triggers a reset if a missing clock condition is detected.
PORSF: Power-On Reset Force and Flag.
Bit 1:
This bit is set anytime a power-on reset occurs. Writing this bit enables/disables the V
DD
Monitor as a reset source. Note: writing ‘1’ to this bit before the V Monitor is enabled
DD
and stabilized may cause a system reset. See register VDM0CN (SFR Definition 12.1)
0: Read: Last reset was not a power-on or V Monitor reset. Write: V Monitor is not a
DD
DD
reset source.
1: Read: Last reset was a power-on or V Monitor reset; all other reset flags
DD
indeterminate. Write: V Monitor is a reset source.
DD
Bit 0:
PINRSF: HW Pin Reset Flag.
0: Source of last reset was not RST pin.
1: Source of last reset was RST pin.
Rev. 1.0
133
SILICON [ SILICON ]
