C8051F360/1/2/3/4/5/6/7/8/9
SFR Definition 12.1. VDM0CN: V Monitor Control
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SFR Page:
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SFR Address: 0xFF
R/W
R
R
R
R
R
R
R
Reset Value
VDMEN VDDSTAT Reserved Reserved Reserved Reserved Reserved Reserved Variable
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit 7:
VDMEN: V Monitor Enable.
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This bit turns the V Monitor circuit on/off. The V Monitor cannot generate system resets
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until it is also selected as a reset source in register RSTSRC (SFR Definition 12.2). The V
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Monitor must be allowed to stabilize before it is selected as a reset source. Selecting the
Monitor as a reset source before it has stabilized may generate a system reset.
V
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0: V Monitor Disabled.
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1: V Monitor Enabled.
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Bit 6:
V
STAT: V Status.
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This bit indicates the current power supply status (V Monitor output).
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0: V is at or below the V Monitor threshold.
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1: V is above the V Monitor threshold.
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Bits 5–0: RESERVED. Read = Variable. Write = don’t care.
12.3. External Reset
The external RST pin provides a means for external circuitry to force the device into a reset state. Assert-
ing an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of the RST
pin may be necessary to avoid erroneous noise-induced resets. See Table 12.1 for complete RST pin
specifications. The PINRSF flag (RSTSRC.0) is set on exit from an external reset.
12.4. Missing Clock Detector Reset
The Missing Clock Detector (MCD) is a one-shot circuit that is triggered by the system clock. If the system
clock remains high or low for more than 100 µs, the one-shot will time out and generate a reset. After a
MCD reset, the MCDRSF flag (RSTSRC.2) will read ‘1’, signifying the MCD as the reset source; otherwise,
this bit reads ‘0’. Writing a ‘1’ to the MCDRSF bit enables the Missing Clock Detector; writing a ‘0’ disables
it. The state of the RST pin is unaffected by this reset.
12.5. Comparator0 Reset
Comparator0 can be configured as a reset source by writing a ‘1’ to the C0RSEF flag (RSTSRC.5).
Comparator0 should be enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on
chatter on the output from generating an unwanted reset. The Comparator0 reset is active-low: if the non-
inverting input voltage (on CP0+) is less than the inverting input voltage (on CP0-), the device is put into
the reset state. After a Comparator0 reset, the C0RSEF flag (RSTSRC.5) will read ‘1’ signifying
Comparator0 as the reset source; otherwise, this bit reads ‘0’. The state of the RST pin is unaffected by
this reset.
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