C8051F360/1/2/3/4/5/6/7/8/9
SFR Definition 11.7. MAC0ACC3: MAC0 Accumulator Byte 3
SFR Page:
0
SFR Address: 0xD5
R
R
R
R
R
R
R
R
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bits 7–0: Byte 3 (bits 31–24) of MAC0 Accumulator.
Note:The contents of this register should not be changed by software during the first two MAC0 pipeline stages.
SFR Definition 11.8. MAC0ACC2: MAC0 Accumulator Byte 2
SFR Page:
0
SFR Address: 0xD4
R
R
R
R
R
R
R
R
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bits 7–0: Byte 2 (bits 23–16) of MAC0 Accumulator.
Note:The contents of this register should not be changed by software during the first two MAC0 pipeline stages.
SFR Definition 11.9. MAC0ACC1: MAC0 Accumulator Byte 1
SFR Page:
0
SFR Address: 0xD3
R
R
R
R
R
R
R
R
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bits 7–0: Byte 1 (bits 15–8) of MAC0 Accumulator.
Note:The contents of this register should not be changed by software during the first two MAC0 pipeline stages.
Rev. 1.0
125
SILICON [ SILICON ]
