C8051F360/1/2/3/4/5/6/7/8/9
SFR Definition 11.10. MAC0ACC0: MAC0 Accumulator Byte 0
SFR Page:
0
SFR Address: 0xD2
R
R
R
R
R
R
R
R
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bits 7–0: Byte 0 (bits 7–0) of MAC0 Accumulator.
Note:The contents of this register should not be changed by software during the first two MAC0 pipeline stages.
SFR Definition 11.11. MAC0OVR: MAC0 Accumulator Overflow
SFR Page:
0
SFR Address: 0xD6
R
R
R
R
R
R
R
R
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bits 7–0: MAC0 Accumulator Overflow Bits (bits 39–32).
Note:The contents of this register should not be changed by software during the first two MAC0 pipeline stages.
SFR Definition 11.12. MAC0RNDH: MAC0 Rounding Register High Byte
SFR Page:
0
SFR Address: 0xAF
R
R
R
R
R
R
R
R
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bits 7–0: High Byte (bits 15–8) of MAC0 Rounding Register.
126
Rev. 1.0
SILICON [ SILICON ]
