C8051F360/1/2/3/4/5/6/7/8/9
SFR Definition 11.4. MAC0AL: MAC0 A Low Byte
SFR Page:
0
SFR Address: 0xA4
R
R
R
R
R
R
R
R
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bits 7–0: Low Byte (bits 7–0) of MAC0 A Register.
SFR Definition 11.5. MAC0BH: MAC0 B High Byte
SFR Page:
0
SFR Address: 0xF2
R
R
R
R
R
R
R
R
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bits 7–0: High Byte (bits 15–8) of MAC0 B Register.
SFR Definition 11.6. MAC0BL: MAC0 B Low Byte
SFR Page:
0
SFR Address: 0xF1
R
R
R
R
R
R
R
R
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bits 7–0: Low Byte (bits 7–0) of MAC0 B Register.
A write to this register initiates a Multiply or Multiply and Accumulate operation.
Note:The contents of this register should not be changed by software during the first MAC0 pipeline stage.
124
Rev. 1.0
SILICON [ SILICON ]
