C8051F360/1/2/3/4/5/6/7/8/9
SFR Definition 11.1. MAC0CF: MAC0 Configuration
SFR Page:
0
SFR Address: 0xD7
R
R
–
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
–
MAC0SC MAC0SD MAC0CA MAC0SAT MAC0FM MAC0MS 00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bits 7–6: UNUSED: Read = 00b, Write = don’t care.
Bit 5:
Bit 4:
Bit 3:
MAC0SC: Accumulator Shift Control.
When set to 1, the 40-bit MAC0 Accumulator register will be shifted during the next SYSCLK
cycle. The direction of the shift (left or right) is controlled by the MAC0SD bit.
This bit is cleared to ‘0’ by hardware when the shift is complete.
MAC0SD: Accumulator Shift Direction.
This bit controls the direction of the accumulator shift activated by the MAC0SC bit.
0: MAC0 Accumulator will be shifted left.
1: MAC0 Accumulator will be shifted right.
MAC0CA: Clear Accumulator.
This bit is used to reset MAC0 before the next operation.
When set to ‘1’, the MAC0 Accumulator will be cleared to zero and the MAC0 Status register
will be reset during the next SYSCLK cycle.
This bit will be cleared to ‘0’ by hardware when the reset is complete.
MAC0SAT: Saturate Rounding Register.
Bit 2:
This bit controls whether the Rounding Register will saturate. If this bit is set and a Soft
Overflow occurs, the Rounding Register will saturate. This bit does not affect the operation
of the MAC0 Accumulator. See Section 11.6 for more details about rounding and saturation.
0: Rounding Register will not saturate.
1: Rounding Register will saturate.
Bit 1:
Bit 0:
MAC0FM: Fractional Mode.
This bit selects between Integer Mode and Fractional Mode for MAC0 operations.
0: MAC0 operates in Integer Mode.
1: MAC0 operates in Fractional Mode.
MAC0MS: Mode Select
This bit selects between MAC Mode and Multiply Only Mode.
0: MAC (Multiply and Accumulate) Mode.
1: Multiply Only Mode.
Note:The contents of this register should not be changed by software during the first two MAC0 pipeline stages.
122
Rev. 1.0
SILICON [ SILICON ]
