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C8051F363 参数 Datasheet PDF下载

C8051F363图片预览
型号: C8051F363
PDF下载: 下载PDF文件 查看货源
内容描述: 混合信号ISP功能的Flash MCU系列 [Mixed Signal ISP Flash MCU Family]
分类和应用:
文件页数/大小: 288 页 / 2659 K
品牌: SILICON [ SILICON ]
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C8051F360/1/2/3/4/5/6/7/8/9  
11.3. Operating in Multiply and Accumulate Mode  
MAC0 operates in Multiply and Accumulate (MAC) mode when the MAC0MS bit (MAC0CF.0) is cleared to  
‘0’. When operating in MAC mode, MAC0 performs a 16-by-16 bit multiply on the contents of the MAC0A  
and MAC0B registers, and adds the result to the contents of the 40-bit MAC0 accumulator. Figure 11.4  
shows the MAC0 pipeline. There are three stages in the pipeline, each of which takes exactly one SYSCLK  
cycle to complete. The MAC operation is initiated with a write to the MAC0BL register. After the MAC0BL  
register is written, MAC0A and MAC0B are multiplied on the first SYSCLK cycle. During the second stage  
of the MAC0 pipeline, the results of the multiplication are added to the current accumulator contents, and  
the result of the addition is stored in the MAC0 accumulator. The status flags in the MAC0STA register are  
set after the end of the second pipeline stage. During the second stage of the pipeline, the next multiplica-  
tion can be initiated by writing to the MAC0BL register, if it is desired. The rounded (and optionally, satu-  
rated) result is available in the MAC0RNDH and MAC0RNDL registers at the end of the third pipeline  
stage. If the MAC0CA bit (MAC0CF.3) is set to ‘1’ when the MAC operation is initiated, the accumulator  
and all MAC0STA flags will be cleared during the next cycle of the controller’s clock (SYSCLK). The  
MAC0CA bit will clear itself to ‘0’ when the clear operation is complete.  
MAC0 Operation  
Begins  
Accumulator  
Results Available  
Rounded Results  
Available  
Write  
Multiply  
MAC0BL  
Add  
Round  
Write  
MAC0BL  
Multiply  
Add  
Round  
Next MAC0  
Operation May  
Be Initiated  
Here  
Figure 11.4. MAC0 Pipeline  
11.4. Operating in Multiply Only Mode  
MAC0 operates in Multiply Only mode when the MAC0MS bit (MAC0CF.0) is set to ‘1’. Multiply Only mode  
is identical to Multiply and Accumulate mode, except that the multiplication result is added with a value of  
zero before being stored in the MAC0 accumulator (i.e. it overwrites the current accumulator contents).  
The result of the multiplication is available in the MAC0 accumulator registers at the end of the second  
MAC0 pipeline stage (two SYSCLKs after writing to MAC0BL). As in MAC mode, the rounded result is  
available in the MAC0 Rounding Registers after the third pipeline stage. Note that in Multiply Only mode,  
the MAC0HO flag is not affected.  
11.5. Accumulator Shift Operations  
MAC0 contains a 1-bit arithmetic shift function which can be used to shift the contents of the 40-bit accu-  
mulator left or right by one bit. The accumulator shift is initiated by writing a ‘1’ to the MAC0SC bit  
(MAC0CF.5), and takes one SYSCLK cycle (the rounded result is available in the MAC0 Rounding Regis-  
ters after a second SYSCLK cycle, and MAC0SC is cleared to ‘0’). The direction of the arithmetic shift is  
controlled by the MAC0SD bit (MAC0CF.4). When this bit is cleared to ‘0’, the MAC0 accumulator will shift  
left. When the MAC0SD bit is set to ‘1’, the MAC0 accumulator will shift right. Right-shift operations are  
sign-extended with the current value of bit 39. Note that the status flags in the MAC0STA register are not  
affected by shift operations.  
Rev. 1.0  
119