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C8051F363 参数 Datasheet PDF下载

C8051F363图片预览
型号: C8051F363
PDF下载: 下载PDF文件 查看货源
内容描述: 混合信号ISP功能的Flash MCU系列 [Mixed Signal ISP Flash MCU Family]
分类和应用:
文件页数/大小: 288 页 / 2659 K
品牌: SILICON [ SILICON ]
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C8051F360/1/2/3/4/5/6/7/8/9  
9.4.7. Register Descriptions  
Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits  
should not be set to logic ‘1’. Future product versions may use these bits to implement new features in  
which case the reset value of the bit will be logic ‘0’, selecting the feature's default state. Detailed descrip-  
tions of the remaining SFRs are included in the sections of the data sheet associated with their corre-  
sponding system function.  
SFR Definition 9.5. SP: Stack Pointer  
SFR Page:  
all pages  
SFR Address: 0x81  
R/W  
R/W  
Bit6  
R/W  
Bit5  
R/W  
Bit4  
R/W  
Bit3  
R/W  
Bit2  
R/W  
Bit1  
R/W  
Bit0  
Reset Value  
00000111  
Bit7  
Bits 7–0: SP: Stack Pointer.  
The Stack Pointer holds the location of the top of the stack. The stack pointer is incremented  
before every PUSH operation. The SP register defaults to 0x07 after reset.  
SFR Definition 9.6. DPL: Data Pointer Low Byte  
SFR Page  
all pages  
SFR Address: 0x82  
R/W  
R/W  
Bit6  
R/W  
Bit5  
R/W  
Bit4  
R/W  
Bit3  
R/W  
Bit2  
R/W  
Bit1  
R/W  
Bit0  
Reset Value  
00000000  
Bit7  
Bits 7–0: DPL: Data Pointer Low.  
The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indirectly  
addressed XRAM and Flash memory.  
SFR Definition 9.7. DPH: Data Pointer High Byte  
SFR Page:  
all pages  
SFR Address: 0x83  
R/W  
R/W  
Bit6  
R/W  
Bit5  
R/W  
Bit4  
R/W  
Bit3  
R/W  
Bit2  
R/W  
Bit1  
R/W  
Bit0  
Reset Value  
00000000  
Bit7  
Bits 7–0: DPH: Data Pointer High.  
The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indirectly  
addressed XRAM and Flash memory.  
102  
Rev. 1.0