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C8051F363 参数 Datasheet PDF下载

C8051F363图片预览
型号: C8051F363
PDF下载: 下载PDF文件 查看货源
内容描述: 混合信号ISP功能的Flash MCU系列 [Mixed Signal ISP Flash MCU Family]
分类和应用:
文件页数/大小: 288 页 / 2659 K
品牌: SILICON [ SILICON ]
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C8051F360/1/2/3/4/5/6/7/8/9  
SFR Definition 9.8. PSW: Program Status Word  
SFR Page:  
SFR Address: 0xD0  
all pages  
(bit addressable)  
R/W  
R/W  
AC  
Bit6  
R/W  
F0  
R/W  
RS1  
Bit4  
R/W  
RS0  
Bit3  
R/W  
OV  
Bit2  
R/W  
F1  
R
Reset Value  
CY  
Bit7  
PARITY 00000000  
Bit5  
Bit1  
Bit0  
Bit 7:  
Bit 6:  
Bit 5:  
CY: Carry Flag.  
This bit is set when the last arithmetic operation resulted in a carry (addition) or a borrow  
(subtraction). It is cleared to 0 by all other arithmetic operations.  
AC: Auxiliary Carry Flag  
This bit is set when the last arithmetic operation resulted in a carry into (addition) or a borrow  
from (subtraction) the high order nibble. It is cleared to 0 by all other arithmetic operations.  
F0: User Flag 0.  
This is a bit-addressable, general purpose flag for use under software control.  
Bits 4–3: RS1–RS0: Register Bank Select.  
These bits select which register bank is used during register accesses.  
RS1  
RS0  
Register Bank  
Address  
0
0
0
0x00–0x07  
0
1
1
1
0
1
1
2
3
0x08–0x0F  
0x10–0x17  
0x18–0x1F  
Bit 2:  
OV: Overflow Flag.  
This bit is set to 1 under the following circumstances:  
• An ADD, ADDC, or SUBB instruction causes a sign-change overflow.  
• A MUL instruction results in an overflow (result is greater than 255).  
• A DIV instruction causes a divide-by-zero condition.  
The OV bit is cleared to 0 by the ADD, ADDC, SUBB, MUL, and DIV instructions in all other  
cases.  
Bit 1:  
Bit 0:  
F1: User Flag 1.  
This is a bit-addressable, general purpose flag for use under software control.  
PARITY: Parity Flag.  
This bit is set to 1 if the sum of the eight bits in the accumulator is odd and cleared if the sum  
is even.  
Rev. 1.0  
103