C8051F360/1/2/3/4/5/6/7/8/9
Table 9.3. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved.
Register
Address
SFR
Description
Page No.
Page
SP
0x81
0xA1
0xA2
0xF8
0xA3
0x88
0x8C
0x8D
0x8A
0x8B
0x89
0xC8
0xCD
0xCC
0xCB
0xCA
0x91
0x95
0x94
0x93
0x92
0xFF
0xE1
0xE2
All Pages Stack Pointer
page 102
page 241
page 243
page 242
page 243
page 252
page 255
page 255
page 255
page 255
page 253
page 258
page 259
page 259
page 259
page 259
page 262
page 263
page 263
page 263
page 263
page 131
page 188
page 189
SPI0CFG
SPI0CKR
SPI0CN
SPI0DAT
TCON
All Pages SPI Configuration
All Pages SPI Clock Rate Control
All Pages SPI Control
All Pages SPI Data
All Pages Timer/Counter Control
All Pages Timer/Counter 0 High Byte
All Pages Timer/Counter 1 High Byte
All Pages Timer/Counter 0 Low Byte
All Pages Timer/Counter 1 Low Byte
All Pages Timer/Counter Mode
TH0
TH1
TL0
TL1
TMOD
TMR2CN
TMR2H
TMR2L
TMR2RLH
TMR2RLL
TMR3CN
TMR3H
TMR3L
TMR3RLH
TMR3RLL
VDM0CN
XBR0
All Pages Timer/Counter 2 Control
All Pages Timer/Counter 2 High Byte
All Pages Timer/Counter 2 Low Byte
All Pages Timer 2 Reload Register High Byte
All Pages Timer 2 Reload Register Low Byte
All Pages Timer 3 Control
All Pages Timer 3 High Byte
All Pages Timer 3 Low Byte
All Pages Timer 3 Reload Register High Byte
All Pages Timer 3 Reload Register Low Byte
All Pages V Monitor Control
DD
F
F
Port I/O Crossbar Control 0
Port I/O Crossbar Control 1
XBR1
Notes:
1. Refers to a register in the C8051F360/1/2/6/7/8/9 only.
2. Refers to a register in the C8051F360/3 only.
Rev. 1.0
101
SILICON [ SILICON ]
