C8051F360/1/2/3/4/5/6/7/8/9
SFR Definition 9.11. PCON: Power Control
SFR Page:
all pages
SFR Address: 0x87
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STOP
Bit1
R/W
IDLE
Bit0
Reset Value
Reserved Reserved Reserved Reserved Reserved Reserved
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bits 7–3: RESERVED. Read = 000000b. Must Write 000000b.
Bit 1:
STOP: STOP Mode Select.
Writing a ‘1’ to this bit will place the CIP-51 into STOP mode. This bit will always read ‘0’.
1: CIP-51 forced into power-down mode. (Turns off oscillator).
IDLE: IDLE Mode Select.
Bit 0:
Writing a ‘1’ to this bit will place the CIP-51 into IDLE mode. This bit will always read ‘0’.
1: CIP-51 forced into IDLE mode. (Shuts off clock to CPU, but clock to Timers, Interrupts,
and all peripherals remain active.)
106
Rev. 1.0
SILICON [ SILICON ]
