8M (512K × 16, 1M × 8) Flash Memory
LH28F800SU
The LH28F800SU incorporates an Automatic Power
Saving (APS) feature which substantially reduces the
active current when the device is in static mode of
operation (addresses not switching).
MEMORY MAP
FFFFFH
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
64KB BLOCK
15
14
13
12
11
10
9
In APS mode, the typical I current is 2 mA at 5.0V
(1 mA at 3.3 V).
CC
F0000H
EFFFFH
E0000H
DFFFFH
A Deep Power-Down mode of operation is invoked
when the RP» (called PWD on the LH28F008SA) pin
transitions low, any current operation is aborted and the
device is put into the deep power-down mode.This mode
brings the device power consumption to less than 5 µA,
typically, and provides additional write protection by
acting as a device reset pin during power transitions.
When the power is turned on, RP» pin turned to low or-
der to return the device to default configuration. When
the 3/5» pin is switched, or when the power transition is
occurred, or at the power on/off, RP» is required to stay
low in order to protect data from noise. A recovery time
D0000H
CFFFFH
C0000H
BFFFFH
B0000H
AFFFFH
A0000H
9FFFFH
90000H
8FFFFH
8
80000H
7FFFFH
of 400 ns (V
= 5.0 V ± 0.5 V) is required from RP»
CC
7
70000H
6FFFFH
switching high until outputs are again valid. In the Deep
Power-Down state, the WSM is reset (any current
operation will abort) and the CSR, GSR and BSR regis-
ters are cleared.
6
60000H
5FFFFH
5
50000H
4FFFFH
A CMOS Standby mode of operation is enabled when
either CE »0 or CE »1 transitions high and RP » stays
high with all input control pins at CMOS levels. In this
4
40000H
3FFFFH
3
30000H
2FFFFH
mode, the device typically draws an I
rent of 10 µA.
standby cur-
CC
2
20000H
1FFFFH
1
10000H
0FFFFH
0
00000H
28F800SUR-3
Figure 4. LH28F800SU Memory Map
(Byte-Wide Mode)
7
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