8M (512K × 16, 1M × 8) Flash Memory
LH28F800SU
DQ8 - DQ15
DQ0 - DQ7
OUTPUT
BUFFER
OUTPUT
BUFFER
INPUT
BUFFER
INPUT
BUFFER
DATA
QUEUE
REGISTERS
ID
REGISTER
3/5
I/O
LOGIC
CSR
OUTPUT
BYTE
MULTIPLEXER
PAGE
BUFFERS
CE0
CE1
ESRs
OE
CUI
WE
WP
RP
DATA
COMPARATOR
INPUT
BUFFER
A0 - A19
Y GATING/SENSING
Y-DECODER
X-DECODER
RY/BY
WSM
ADDRESS
QUEUE
LATCHES
. . .
. . .
PROGRAM/
ERASE
VOLTAGE
SWITCH
VPP
3/5
ADDRESS
COUNTER
VCC
GND
28F800SUR-2
Figure 3. LH28F800SU Block Diagram (Architectural Evolution Includes Page Buffers,
Queue Registers and Extended Status Registers)
3