LH28F800SU
8M (512K × 16, 1M × 8) Flash Memory
LH28F008SA-Compatible Mode Command Bus Definitions
FIRST BUS CYCLE
COMMAND
SECOND BUS CYCLE
NOTE
OPER.
Write
Write
Write
Write
Write
Write
Write
Write
ADDRESS
DATA
FFH
90H
70H
50H
40H
10H
20H
B0H
OPER.
Read
Read
Read
ADDRESS
DATA
Read Array
X
X
X
X
X
X
X
X
AA
IA
X
AD
Intelligent Identifier
ID
1
2
3
Read Compatible Status Register
Clear Status Register
Word/Byte Write
CSRD
Write
Write
Write
Write
WA
WA
BA
X
WD
WD
Alternate Word/Byte Write
Block Erase/Confirm
Erase Suspend/Resume
D0H
D0H
ADDRESS
DATA
AA = Array Address
BA = Block Address
IA = Identifier Address
WA = Write Address
X = Don’t Care
AD = Array Data
CSRD = CSR Data
ID = Identifier Data
WD = Write Data
NOTES:
1. Following the intelligent identifier command, two Read operations access the manufacturer and device signature codes.
2. The CSR is automatically available after device enters Data Write, Erase or Suspend operations.
3. Clears CSR.3, CSR.4, and CSR.5. Also clears GSR.5 and all BSR.5 and BSR.2 bits. See Status register definitions.
10
SHARP [ SHARP ELECTRIONIC COMPONENTS ]
