8M (512K × 16, 1M × 8) Flash Memory
LH28F800SU
LH28F800SU Performance Enhancement Command Bus Definitions
FIRST BUS CYCLE
SECOND BUS CYCLE
THIRD BUS CYCLE
COMMAND
MODE
NOTE
OPER. ADDR. DATA OPER. ADDR. DATA OPER. ADDR.
DATA
Read Extended
Status Register
GSRD
BSRD
Write
X
71H
Read
RA
1
7
Page Buffer Swap
Read Page Buffer
Write
Write
X
X
72H
75H
Read
Write
Write
Write
PA
PA
X
PD
PD
Single Load to
Page Buffer
Write
Write
Write
X
X
X
74H
E0H
E0H
x8
BCL
WCL
Write
Write
X
X
BCH
4, 6, 10
Sequential Load to
Page Buffer
4, 5,
6, 10
x16
X
WCH
BC
(L, H)
3, 4,
9, 10
x8
x16
x8
Write
Write
Write
X
X
X
0CH
0CH
FBH
Write
Write
Write
A0
X
Write
Write
Write
WA
WA
WA
BC (H, L)
WCH
Page Buffer Write
to Flash
WCL
4, 5, 10
3
WD
(L, H)
Two-Byte Write
A0
WD(H, L)
Block
Erase/Confirm
Write
Write
Write
X
X
X
20H
77H
97H
Write
Write
Write
BA
BA
X
D0H
D0H
D0H
Lock Block/Confirm
Upload Status
Bits/Confirm
2
Upload Device
Information
Write
Write
Write
Write
Write
X
X
X
X
X
99H
A7H
96H
96H
96H
Write
Write
Write
Write
X
X
X
X
D0H
D0H
01H
02H
Erase All Unlocked
Blocks/Confirm
RY»/BY» Enable to
Level-Mode
8
8
RY»/BY» Pulse-On-
Write
RY»/BY» Pulse-On-
Erase
Write
Write
X
X
03H
04H
8
8
RY»/BY» Disable
Sleep
Write
Write
Write
X
X
X
96H
F0H
80H
Abort
ADDRESS
BA = Block Address
PA = Page Buffer Address
RA = Extended Register Address
WA = Write Address
DATA
AD = Array Data
PD = Page Buffer Data
BSRD = BSR Data
GSRD = GSR Data
X = Don’t Care
WC (L, H) = Word Count (Low, High)
BC (L, H) = Byte Count (Low, High)
WD (L, H) = Write Data (Low, High)
11
SHARP [ SHARP ELECTRIONIC COMPONENTS ]
