8M (512K × 16, 1M × 8) Flash Memory
LH28F800SU
WRITE VALID
WRITE
DATA-WRITE
OR ERASE
SETUP COMMAND
ADDRESS AND DATA AUTOMATED
WRITE READ
EXTENDED
REGISTER
COMMAND
READ
EXTENDED
STATUS
(DATA-WRITE) OR
ERASE CONFIRM
COMMAND
DATA-WRITE
OR ERASE
DELAY
DEEP
POWER-DOWN
REGISTER DATA
VIH
ADDRESSES (A)
AIN
A = RA
(NOTE 1)
VIL
READ
COMPATIBLE
STATUS
tAVAV
tAVWH
tWHAX
REGISTER DATA
(NOTE 3)
VIH
VIL
ADDRESSES (A)
(NOTE 2)
AIN
A = RA
tAVWH tWHAX
tAVAV
CEX (E)
(NOTE 4)
VIH
VIL
tWHGL
tWHEH
tELWL
VIH
VIL
OE (G)
tWHWL
tWHQV1, 2
tGHWL
VIH
VIL
WE (W)
tWLWH
tWHDX
tDVWH
VIH
VIL
HIGH-Z
tPHWL
DATA (D/Q)
DIN
DIN
DIN
DOUT
DIN
tWHRL
VOH
VOL
RY/BY (R)
RP (P)
tRHPL
VIH
VIL
(NOTE 5)
tQVVL
tVPWH
VPPH
VPPL
VPP (V)
NOTES:
1. This address string depicts Data-Write/Erase cycles with corresponding verification via ESRD.
2. This address string depicts Data-Write/Erase cycles with corresponding verification via CSRD.
3. This cycle is invalid when using CSRD for verification during Data-Write/Erase operations.
4. CEX is defined as the latter of CE0 or CE1 going LOW or the first of CE0 or CE1 going HIGH.
5. RP low transition is only to show tRHPL; not valid for above Read and Write cycles.
28F800SUR-13
Figure 15. AC Waveforms for Command Write Operations
31
SHARP [ SHARP ELECTRIONIC COMPONENTS ]
