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LH28F800SUT-70 参数 Datasheet PDF下载

LH28F800SUT-70图片预览
型号: LH28F800SUT-70
PDF下载: 下载PDF文件 查看货源
内容描述: 8M ( 512K × 16 , 1M × 8 )快闪记忆体 [8M (512K 】 16, 1M 】 8) Flash Memory]
分类和应用: 闪存存储内存集成电路光电二极管
文件页数/大小: 38 页 / 327 K
品牌: SHARP [ SHARP ELECTRIONIC COMPONENTS ]
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LH28F800SU  
8M (512K × 16, 1M × 8) Flash Memory  
1
AC Characteristics for WE  
»
- Controlled Command Write Operations (Continued)  
T = 0°C to +70°C  
A
VCC = 5.0 ± 0.25 V  
VCC = 5.0 ± 0.5 V  
SYMBOL  
PARAMETER  
UNITS  
NOTE  
TYP. MIN. MAX. TYP. MIN. MAX.  
tAVAV  
tVPWH  
tPHEL  
Write Cycle Time  
70  
100  
480  
0
80  
100  
480  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
VPP Setup to WE Going High  
RP» Setup to CE» Going Low  
CE» Setup to WE Going Low  
Address Setup to WE Going High  
Data Setup to WE Going High  
WE Pulse Width  
3
tELWL  
tAVWH  
tDVWH  
tWLWH  
tWHDX  
tWHAX  
tWHEH  
tWHWL  
tGHWL  
tWHRL  
50  
50  
40  
0
50  
50  
50  
0
2, 6  
2, 6  
Data Hold from WE High  
Address Hold from WE High  
CE» Hold from WE High  
2
2
10  
10  
30  
0
10  
10  
30  
0
WE Pulse Width High  
Read Recovery before Write  
WE High to RY/» BY» Going Low  
100  
100  
RP» Hold from Valid Status Register  
(CSR, GSR, BSR) Data and RY/» BY» High  
tRHPL  
0
0
ns  
3
tPHWL  
tWHGL  
RP» High Recovery to WE Going Low  
1
1
µs  
ns  
Write Recovery before Read  
60  
65  
VPP Hold from Valid Status Register (CSR,  
GSR, BSR) Data and RY/» BY» High  
tQVVL  
0
0
µs  
1
tWHQV  
Duration of Word/Byte Write Operation  
Duration of Block Erase Operation  
8
4.5  
0.3  
8
4.5  
0.3  
µs  
s
4, 5  
4
2
tWHQV  
NOTES:  
CE» is defined as the latter of CE»0 or CE» going Low or the first of CE»0 or CE»1 going High.  
1
1. Read timing during write and erase are the same as for normal read.  
2. Refer to command definition tables for valid address and data values.  
3. Sampled, but not 100% tested.  
4. Write/Erase durations are measured to valid Status Register (CSR) Data.  
5. Word/Byte write operations are typically performed with 1 Programming Pulse.  
6. Address and Data are latched on the rising edge of CE» for all Command Write Operations.  
30  
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