8M (512K × 16, 1M × 8) Flash Memory
LH28F800SU
56-PIN TSOP
TOP VIEW
FEATURES
• User-Configurable x8 or x16 Operation
WP
WE
OE
56
55
54
1
3/5
• User-Selectable 3.3 V or 5 V V
CC
2
CE1
NC
3
4
5
6
7
8
9
• 5 V Write/Erase Operations (5 V V )
PP
53
52
RY/BY
DQ15
DQ7
NC
A19
– No Requirement for DC/DC
Converter to Write/Erase
A18
A17
51
50
• 70 ns Maximum Access Time
DQ14
DQ6
• Minimum 2.7 V Read capability
A16
49
48
47
46
45
44
43
42
41
40
39
38
37
– 160 ns Maximum Access Time
GND
DQ13
DQ5
VCC
10
11
12
13
14
(V = 2.7 V)
A15
A14
A13
A12
CC
• 16 Independently Lockable Blocks
• 0.32 MB/sec Write Transfer Rate
• 100,000 Erase Cycles per Block
DQ12
DQ4
VCC
CE0
VPP
RP
A11
A10
A9
15
16
17
18
GND
DQ11
DQ3
• Revolutionary Architecture
– Pipelined Command Execution
– Write During Erase
DQ10
– Command Superset of
Sharp LH28F008SA
19
20
21
DQ2
VCC
A8
GND
A7
DQ9
DQ1
36
35
34
33
32
31
• 5 µA (TYP.) I in CMOS Standby
CC
22
23
24
25
• 1 µA (TYP.) Deep Power-Down
A6
DQ8
DQ0
A0
A5
• State-of-the-Art 0.55 µm ETOX™
A4
Flash Technology
26
27
28
BYTE
A3
• 56-Pin, 1.2 mm × 14 mm × 20 mm
A2
30
29
NC
NC
TSOP (Type I) Package
A1
28F800SUR-1
Figure 1. TSOP Reverse Bend Configuration
1
SHARP [ SHARP ELECTRIONIC COMPONENTS ]
