LH28F800SU
8M (512K × 16, 1M × 8) Flash Memory
56-PIN TSOP
TOP VIEW
INTRODUCTION
Sharp’s LH28F800SU 8M Flash Memory is a revolu-
tionary architecture which enables the design of truly
mobile, high performance, personal computing and com-
munication products. With innovative capabilities, 5 V
single voltage operation and very high read/write per-
formance, the LH28F800SU is also the ideal choice for
designing embedded mass storage flash memory sys-
tems.
1
2
3
4
3/5
CE1
NC
56
55
54
53
52
WP
WE
OE
NC
RY/BY
DQ15
5
6
7
8
9
A19
A18
A17
DQ7
DQ14
DQ6
51
50
The LH28F800SU is a very high density, highest per-
formance non-volatile read/write solution for solid-state
storage applications. Its symmetrically blocked archi-
tecture (100% compatible with the LH28F008SA 8M
Flash memory, the LH28F016SA 16M Flash memory
and the LH28F016SU 16M 5 V single voltage Flash
memory), extended cycling, low power 3.3V operation,
very fast write and read performance and selective block
locking provide a highly flexible memory component suit-
able for high density memory cards, Resident Flash
Arrays and PCMCIA-ATA Flash Drives. The
LH28F800SU’s dual read voltage enables the design of
memory cards which can interchangeably be read/writ-
ten in 3.3 V and 5.0 V systems. Its x8/x16 architecture
allows the optimization of memory to processor inter-
face.The flexible block locking option enables bundling
of executable application software in a Resident Flash
Array or memory card. Manufactured on Sharp’s 0.55
µm ETOX™ process technology, the LH28F800SU is
the most cost-effective, high-density 3.3V flash memory.
A16
49
48
47
46
45
44
43
42
41
40
39
38
37
GND
DQ13
DQ5
VCC
10
11
12
13
14
A15
A14
A13
A12
DQ12
DQ4
VCC
CE0
VPP
RP
A11
A10
A9
15
16
17
18
GND
DQ11
DQ3
DQ10
19
20
21
DQ2
VCC
A8
GND
A7
DQ9
DQ1
36
35
34
33
32
31
22
23
24
25
A6
DQ8
DQ0
A0
A5
A4
DESCRIPTION
26
27
28
A3
BYTE
The LH28F800SU is a high performance 8M
(8,388,608 bit) block erasable non-volatile random
access memory organized as either 512K × 16 or
1M × 8.The LH28F800SU includes sixteen 64K (65,536)
blocks or sixteen 32-KW (32,768) blocks.A chip memory
map is shown in Figure 3.
A2
30
29
NC
NC
A1
28F800SUR-17
Figure 2. TSOP Configuration
The implementation of a new architecture, with many
enhanced features, will improve the device operating
characteristics and results in greater product reliability
and ease of use.
Among the significant enhancements of the
LH28F800SU:
• 5 V Write/Erase Operation (5 V V
)
PP
• 3.3 V Low Power Capability (2.7 V V Read)
CC
• Improved Write Performance
• Dedicated Block Write/Erase Protection
A 3/5» input pin reconfigures the device internally for
optimized 3.3 V or 5.0 V read/write operation.
2
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