LC89057W-VF4A-E
10.1.8 Output clocks block diagram (RMCK, RBCK, RLRCK, SBCK, SLRCK, XMCK)
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The relationships between the output clock and switch function are shown below.
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PLL in the figure indicates the PLL source (or TMCK source), and XIN the XIN source.
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The contents in the square brackets [∗∗∗] by the switch function blocks correspond to the write command names.
The broken lines connecting the switches indicate coordinated switching.
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Lock/Unlock is switched automatically by PLL locking/unlocking.
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Master/Slave is switched by master/slave function switching of demodulation function.
Lock / Unlock
[OCKSEL] ([SELMTD]=0)
[PRSEL]
512fs / 256fs
256fs / 128fs
128fs / 64fs
MUTE
Master Clock
[RCKSEL] ([SELMTD]=1)
Generator
PLL
XIN
XTAL Source
12.288MHz or 24.576MHz
RMCK (O)
12.288MHz / 24.576MHz
6.144MHz / 12.288MHz
3.072MHz / 6.144MHz
MUTE
[XRSEL]
PLL Source
256fs or 512fs
TMCK Source
256fs or 512fs
PLL 64fs
Master / Slave
PLL
XIN
RBCK (I/O)
12.288MHz
6.144MHz
3.072MHz
[XRBCK]
MUTE
PLL fs
[XRLRCK]
PLL
XIN
RLRCK (I/O)
192kHz
96kHz
48kHz
MUTE
to internal circuits
128fs
64fs
[PSBCK]
32fs
MUTE
[SELMTD]
PLL
XIN
SBCK (O)
12.288MHz
6.144MHz
3.072MHz
MUTE
[XSBCK]
2fs
fs
[PSLRCK]
fs/2
MUTE
PLL
XIN
SLRCK (O)
192kHz
96kHz
48kHz
MUTE
[XSLRCK]
12.288MHz / 24.576MHz
6.144MHz / 12.288MHz
MUTE
[XMSEL]
XMCK (O)
XIN
Figure 10.3 Clock Output Block Diagram
No.7202-18/59
SANYO [ SANYO SEMICON DEVICE ]
