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LC7218 参数 Datasheet PDF下载

LC7218图片预览
型号: LC7218
PDF下载: 下载PDF文件 查看货源
内容描述: 在AV系统的PLL频率合成器的电子调谐 [PLL Frequency Synthesizer for Electronic Tuning in AV Systems]
分类和应用: 光电二极管电子
文件页数/大小: 16 页 / 265 K
品牌: SANYO [ SANYO SEMICON DEVICE ]
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LC7218, 7218M, 7218JM  
Electrical Characteristics for the Allowable Operating Ranges  
Parameter  
Internal feedback resistance  
Hysteresis  
Symbol  
Rf (1)  
Rf (2)  
Rf (3)  
Rf (4)  
Rf (5)  
Conditions  
min  
typ  
1.0  
max  
Unit  
MΩ  
kΩ  
kΩ  
kΩ  
kΩ  
V
XIN  
FMIN  
AMIN  
HCTR  
LCTR  
LCTR  
500  
500  
500  
500  
V
H
0.1 V  
0.6 V  
DD  
DD  
I
I
I
I
I
(1)  
(2)  
(3)  
(4)  
(5)  
(1)  
(2)  
(3)  
(4)  
(5)  
CE, CL, DI: V = 6.5 V  
I
5.0  
5.0  
20  
µA  
µA  
µA  
µA  
µA  
µA  
µA  
µA  
µA  
µA  
V
IH  
IH  
IH  
IH  
IH  
IN0, IN1: V = V  
I
DD  
Input high level current  
XIN: V = V  
I DD  
FMIN, AMIN: V = V  
40  
I
DD  
HCTR, LCTR: V = V  
I
40  
DD  
I
CE, CL, DI: V = V  
5.0  
5.0  
20  
IL  
IL  
IL  
IL  
IL  
I
SS  
I
IN0, IN1: V = V  
I
SS  
Input low level current  
I
I
I
XIN: V = V  
I
SS  
FMIN, AMIN: V = V  
40  
I
SS  
HCTR, LCTR: V = V  
40  
I
SS  
V
V
(1)  
(2)  
(1)  
(2)  
(3)  
(4)  
(5)  
(6)  
(1)  
(2)  
(3)  
OUT1, OUT2: I = –1 mA  
O
V
V
– 1.0  
– 1.0  
OH  
OH  
DD  
DD  
Output high level voltage  
PD1, PD2: I = –0.5 mA  
O
V
V
V
V
V
V
V
OUT1, OUT2: I = 1 mA  
O
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
5.0  
5.0  
5.0  
V
OL  
OL  
OL  
OL  
OL  
OL  
PD1, PD2: I = 0.5 mA  
O
V
OUT3 to OUT6: I = 5 mA  
O
V
Output low level voltage  
Output off leakage current  
OUT0: I = 1 mA  
O
V
DO: I = 5 mA  
O
V
SYC: I = 0.5 mA (V  
= 3.5 to 6.5 V)  
V
O
DD  
I
I
I
OUT3 to OUT6, OUT0: V = 13 V  
O
µA  
µA  
µA  
OFF  
OFF  
OFF  
DO: V = 6.5 V  
O
SYC: V = 6.5 V (V  
O
= 3.5 to 6.5 V)  
DD  
Three-state high level  
off leakage current  
I
PD1, PD2: V = V  
0.01  
10.0  
nA  
OFFH  
O
DD  
Three-state low level  
off leakage current  
I
PD1, PD2: V = V  
O
0.01  
2
10.0  
3
nA  
pF  
OFFL  
SS  
Input capacitance  
Current drain  
C
FMIN, HCTR  
1
IN  
V
: f (2) = 130 MHz, V (2) = 70 mVrms,  
IN  
DD IN  
I
(1)  
(2)  
with a 7.2 MHz crystal, other input pins at V  
output pins open  
,
20  
30  
mA  
mA  
DD  
SS  
V
: PLL block stopped (PLL inhibit state), crystal  
DD  
I
oscillator operating (SYC, TB), with a 7.2 MHz crystal,  
1.0  
DD  
other input pins at V , output pins open  
SS  
Note: A capacitor of at least 2000 pF must be inserted between the power supply V  
and V potentials.  
SS  
DD  
No. 4758-5/16  
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