INTERRUPT CONTROLLER
S3C4510B
INTERRUPT PENDING BY PRIORITY REGISTER
The interrupt pending by priority register, INTPNDPRI, contains interrupt pending bits, which are re-ordered by
the INTPRIn register settings. INTPNDPRI[20] is mapped to the interrupt source of whichever bit index is written
into the priority 20 field of the INTPRIn registers.
This register is useful for testing. To validate the interrupt pending by priority value, you can obtain the highest
priority pending interrupt from the interrupt offset register, INTOFFSET.
Table 13-7. INTPNDPRI Register
Register
Offset Address
R/W
Description
Reset Value
INTPNDPRI
0x4028
R
Interrupt pending by priority
0x00000000
INTERRUPT PENDING TEST REGISTER
The interrupt pending test register, INTPNDTST, is used to set or clear INTPND and INTPNDPRI. If user writes
data to this register, it is written into both the INTPND register and INTPNDPRI register. The interrupt pending
test register, INTPNDTST, is also useful for testing.
For INTPND, the same bit position is updated with the new coming data. For INTPNDPRI, the mapping bit
position by INTPRIn registers is updated with the new coming data to keep with the contents of the INTPND
register.
Table 13-8. INTPNDTST Register
Register
Offset
R/W
Description
Reset Value
Address
INTPNDTST
0x402C
W
Interrupt pending test register
0x00000000
13-8
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