S3C4510B
INTERRUPT CONTROLLER
INTERRUPT OFFSET REGISTER
The interrupt offset register, INTOFFSET, contains the interrupt offset address of the interrupt, which has the
highest priority among the pending interrupts. The content of the interrupt offset address is "bit position value of
the interrupt source << 2".
If all interrupt pending bits are "0" when you read this register, the return value is "0x00000054".
This register is valid only under the IRQ or FIQ mode in the ARM7TDMI. In the interrupt service routine, you
should read this register before changing the CPU mode.
INTOSET_FIQ/INTOSET_IRQ register can be used to get the highest priority interrupt without CPU mode
change. Other usages are similar to INTOFFSET.
NOTE
If the lowest interrupt priority (priority 0) is pending, the INTOFFSET value will be "0x00000000". The
reset value will, therefore, be changed to "0x00000054" (to be differentiated from interrupt pending
priority 0).
Table 13-6. INTOFFSET Register
Register
Offset
R/W
Description
Reset Value
Address
INTOFFSET
0x4024
0x4030
0x4034
R
R
R
Interrupt offset register
0x00000054
0x00000054
0x00000054
INTOSET_FIQ
INTOSET_IRQ
FIQ interrupt offset register
IRQ interrupt offset register
13-7
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