S3C4510B
INTERRUPT CONTROLLER
INTERRUPT MASK REGISTER
The interrupt mask register, INTMSK, contains interrupt mask bits for each interrupt source.
Table 13-4. INTMSK Register
Register
INTMSK
Offset Address
R/W
Description
Interrupt mask register
Reset Value
0x4008
R/W
0x003FFFFF
31
21 20 19 18 17 16 15 14 13 12 11 10 9
8 7 6 5 4 3 2 1 0
INTMSK
G X X X X X X X X X X X X X X X X X X X X X
[20:0] Individual interrupt mask bits
NOTE:
Each of the 21 bits in the interrupt mask register, INTMSK,
(except for the global mask bit, G) corresponds to an interrupt source.
When a source interrupt mask bit is 1, the interrupt is not serviced by the
CPU when the corresponding interrupt request is generated. If the mask
bit is 0, the interrupt is serviced upon request. And if global mask bit
(bit 21) is 1, no interrupts are serviced. (However, the source pending
bit is set whenever the interrupt is generated.) After the global mask bit
is cleared, the interrupt is serviced. The 21 interrupt sources are mapped
as follows:
[20] I2C interrupt
[19] Ethernet controller MAC Rx interrupt
[18] Ethernet controller MAC Tx interrupt
[17] Ethernet controller BDMA Rx interrupt
[16] Ethernet controller BDMA Tx interrupt
[15] HDLC channel B Rx interrupt
[14] HDLC channel B Tx interrupt
[13] HDLC channel A Rx interrupt
[12] HDLC channel A Tx interrupt
[11] Timer 1 interrupt
[10] Timer 0 interrupt
[9] GDMA channel 1 interrupt
[8] GDMA channel 0 interrupt
[7] UART1 receive and error interrupt
[6] UART1 transmit interrupt
[5] UART0 receive and error interrupt
[4] UART0 transmit interrupt
[3] External interrupt 3
[2] External interrupt 2
[1] External interrupt 1
[0] External interrupt 0
[21] Global interrupt mask bit
0 = Enable interrupt requests
1 = Disable all interrupt requests
Figure 13-3. Interrupt Mask Register (INTMSK)
13-5
SAMSUNG [ SAMSUNG ]
