INTERRUPT CONTROLLER
S3C4510B
INTERRUPT PENDING REGISTER
The interrupt pending register, INTPND, contains interrupt pending bits for each interrupt source. This register
has to be cleared at the top of an interrupt service routine.
Table 13-3. INTPND Register
Register
INTPND
Offset Address
R/W
Description
Interrupt pending register
Reset Value
0x4004
R/W
0x00000000
31
21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
INTPND
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
[20:0] Interrupt pending bits
NOTE:
Each of the 21 bits in the interrupt mode pending register, INTPND,
corresponds to an interrupt source. When an interrupt request is
generated, its pending bit is set to 1. The service routine must then
clear the pending condition by writing a 1 to the apropriate pending
bit at start. The 21 interrupt sources are mapped as follows:
[20] I2C interrupt
[19] Ethernet controller MAC Rx interrupt
[18] Ethernet controller MAC Tx interrupt
[17] Ethernet controller BDMA Rx interrupt
[16] Ethernet controller BDMA Tx interrupt
[15] HDLC channel B Rx interrupt
[14] HDLC channel B Tx interrupt
[13] HDLC channel A Rx interrupt
[12] HDLC channel A Tx interrupt
[11] Timer 1 interrupt
[10] Timer 0 interrupt
[9] GDMA channel 1 interrupt
[8] GDMA channel 0 interrupt
[7] UART1 receive and error interrupt
[6] UART1 transmit interrupt
[5] UART0 receive and error interrupt
[4] UART0 transmit interrupt
[3] External interrupt 3
[2] External interrupt 2
[1] External interrupt 1
[0] External interrupt 0
Figure 13-2. Interrupt Pending Register (INTPND)
13-4
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