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S3C4510B 参数 Datasheet PDF下载

S3C4510B图片预览
型号: S3C4510B
PDF下载: 下载PDF文件 查看货源
内容描述: 三星S3C4510B的16位/ 32位RISC微控制器是一款高性价比,高性能的基于以太网的系统微控制器解决方案。 [Samsungs S3C4510B 16/32-bit RISC microcontroller is a cost-effective, high-performance microcontroller solution for Ethernet-based systems.]
分类和应用: 微控制器以太网
文件页数/大小: 422 页 / 2160 K
品牌: SAMSUNG [ SAMSUNG ]
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UART  
S3C4510B  
UART STATUS REGISTER  
Table 10-6. UCON0 and UCON1 Registers  
Registers  
USTAT0  
Offset Address  
R/W  
R
Description  
UART0 status register  
UART1 status register  
Reset Value  
0xC0  
0xD008  
0xE008  
USTAT1  
R
0xC0  
Table 10-7. UART Status Register Description  
Bit Name Reset Value  
Bit Number  
[0]  
Overrun error  
USTAT[0] is automatically set to "1" whenever an overrun error  
occurs during a serial data receive operation. The overrun error  
indicates that the new received data has overwritten old received  
data before the old data could be read.  
If the receive status interrupt enable bit, UCON[2] is "1", a receive  
status interrupt is generated if an overrun error occurs.  
This bit is automatically cleared to "0" whenever the UART status  
register (USTAT) is read.  
[1]  
[2]  
Parity error  
Frame error  
USTAT[1] is automatically set to "1" whenever a parity error occurs  
during a serial data receive operation. If the receive status interrupt  
enable bit, UCON[2], is "1", a receive status interrupt is generated  
if a parity error occurs.  
This bit is automatically cleared to "0" whenever the UART status  
register (USTAT) is read.  
USTAT[2] is automatically set to "1" whenever a frame error occurs  
during a serial data receive operation. A frame error occurs when a  
zero is detected instead of the Stop bit(s).  
If the receive status interrupt enable bit, UCON[2] is "1", a receive  
status interrupt is generated if a frame error occurs.  
The frame error bit is automatically cleared to "0" whenever the  
UART status register (USTAT) is read.  
[3]  
[4]  
Break interrupt  
USTAT[3] is automatically set to "1" to indicate that a break signal  
has been received.  
If the receive status interrupt enable bit, UCON[2], is "1", a receive  
status interrupt is generated if a break occurs.  
The break interrupt bit is automatically cleared to "0" when you  
read the UART status register.  
Data terminal ready  
(DTR)  
The USTAT[4] bit indicates the current signal level at the data  
terminal ready (DTR) pins (nUADTR). When this bit is "1", the level  
at the DTR pin (nUADTR) is Low. When it is "0", the DTR pin is  
High level.  
10-8  
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