S3C4510B
UART
31
8
7
6
5
4
3
2
1 0
R
x
S
I
L S D
P B S
B K R
TxM
RxM
[1:0] SIO receive mode selection (RxM)
00 = Disable
01 = Interrupt request
10 = GDMA channel 0 request
11 = GDMA channel 1 request
[2] Receive status interrupt enable (RxSI)
0 = Do not generate receive status interrupt
1 = Generate receive status interrupt
[4:3] SIO transmit mode selection (TxM)
00 = Disable
01 = Interrupt request
10 = GDMA channel 0 request
11 = GDMA channel 1 request
[5] Data set ready (DSR)
0 = Deassert S3C4510B DSR output (nUADSR)
1 = Assert S3C4510B DSR output (nUADSR)
[6] Send break (SBK)
0 = Do not send break
1 = Send break
[7] Loop-back enable (LPB)
0 = Normal operation mode
1 = Enable look-up mode (for testing only)
Figure 10-3. UART Control Registers
10-7