S3C4510B
DMA CONTROLLER
DEMAND AND ONE DATA BURST MODE (GDMACON[15] = 1, [9] = 0 )
DREQ and DACK signals are active low.
In_MCLK
DREQ
DACK
Address
Data
S0
D0
S1
D1
S2
D2
S3
D3
GDMA
CNT
8
7
6
5
4
3
2
1
0
NOTE:
S# is source address#, and D# is destination address#.
If GDMA CNT is zero, GDMAC do not transfer data although DREQ signal asserted.
Figure 9-15. Demand and One Data Burst Mode Timing
DEMAND & FOUR DATA BURST MODE ( GDMACON[15] = 1, [9] = 1 )
This timing diagram is the same with Demand & one data burst exception four data burst.
one data burst; source address0 and source data0 ® destination address0 and destination data0 ® ...
four data burst; source address0 and source data0 ® source address1 and source data1 ® source address2 and
source data2 ® source address3 and source data3 ® destination address0 and destination data0
® destination address1 and destination data1 ® destination address2 and destination data2 ®
destination address2 and destination data2 ® destination address3 and destination data3 ® ...
NOTE
If you want to use continuous mode, you must set block mode not single mode.
If you want to use demand mode, you must set single mode not block mode.
9-17
SAMSUNG [ SAMSUNG ]
