S3C4510B
DMA CONTROLLER
SINGLE AND ONE DATA BURST MODE (GDMACON[11] = 0, [9] = 0 )
DREQ and DACK signals are active low.
Recommand
Deasserted Time
In_MCLK
DREQ
DACK
a
b
c
Source
Address
Destination
Address
Address
Data
Source
Data
Destination
data
NOTES:
1. In this region, DMA operation is independent of the number of DREQ signal pulse. For example, although
DREQ signal pulses 3 times in the '¨Í' region, GDMAC transfers data only one time from source address to
destination address. Current DREQ signal is idle state(deasserted) when DACK siganl is idle state
(high). Otherwise, GDMAC recognizes current DREQ signal as next one and transfers next data.
I recommand that DREQ signal is deasserted when DACK signal is active.
2. '¨Î' is three more cycles(3+a cycles). The 'a' is internal system bus acquistion time.
3. '¨Ï' signal falls at negative edge In_MCLK clock after source data is valid.
Figure 9-11. Single and One Data Burst Mode Timing
9-13
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