S3C4510B
DMA CONTROLLER
BLOCK AND ONE DATA BURST MODE (GDMACON[11] = 1, [9] = 0 )
DREQ and DACK signals are active low.
GDMAC transfers data from DREQ signal is active till GDMA COUNT Register consumes.
Recommand
Deasserted Time
In_MCLK
DREQ
DACK
a
Source
Address
Destination
Address
Source
Address
Destination
Address
Address
Data
Source
Data
Destination
Data
Source
Data
Destination
Data
NOTE:
'¨Í' is in the block mode, GDMAC starts to operate with first DREQ signal. So in the ideal case,
GDMAC don't care the number of DREQ signal pulse. But I recommand that DREQ siganl is
deasserted when DACK signal is active state.
Figure 9-13. Block and One Data Burst Mode Timing
BLOCK AND FOUR DATA BURST (GDMACON[11] = 1, [9] = 1 )
This timing diagram is the same with Single and one data burst exception four data burst.
one data burst; source address0 and source data0 ® destination address0 and destination data0 ® ....
four data burst; source address0 and source data0 ® source address1 and source data1 ® source address2 and
source data2 ® source address3 and source data3 ® destination address0 and destination data0
® destination address1 and destination data1 ® destination address2 and destination data2 ®
destination address3 and destination data3 ® source address4 and source data4 ® ....
NOTE
In the four data burst mode, GDMA COUNT Register value decreases by 1 after 4 data transfer.
9-15
SAMSUNG [ SAMSUNG ]
