DMA CONTROLLER
S3C4510B
SINGLE AND FOUR DATA BURST MODE (GDMACON[11] = 0, [9] = 1 )
DREQ & DACK signals are active low.
In the four data burst mode, GDMA COUNT Register(GDMA CNT) value decreases by 1 after 4 data transfer.
Recommand
Deasserted Time
In_MCLK
DREQ
DACK
Address
Data
S0
S1
S2
S3
D0
D1
D2
D3
S4
GDMA
CNT
N
N-1
NOTE:
Address order is source address0 -> source address1 -> source address 2 -> source address3
-> destination address0 -> destination address1 ->destination address2 -> destination
address3, and Data order is source data0 -> source data1 -> source data2 -> source data3
-> destination data0 -> destination data1 -> destination data2 -> destination data3.
Figure 9-12. Single and Four Data Burst Mode Timing
9-14