S3C4510B
HDLC CONTROLLERS
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4 3 2 1 0
A R T R T T T
R T T T D D D
R
x
W
A
R T B
R
x
D D D
P R T
T D D R T
x R T
T
x
u
t
x
x
x
x
x
x
x
x
x
x R R T
x
4
x R
4 G
x x
N N D D P A
E L S F
x
x
x
E
L
x
x
E x x R R
A
B
T
E
X
T
o O O
I
T R B
C O F L M S S
H O L A A T T
O P A G D S S
W W E
D D N
N N R R S S
S S
L E E
E N N
N
E C C S R M T
N R R C
C C O
N
B
G
E K K
C
[0] Tx reset (TxRS)
0 = Normal
[1] Rx reset (RxRS)
0 = Normal operation
[2] DMA Tx reset (DTxRS)
0 = Normal operation
[3] DMA Rx reset (DRxRS)
0 = Normal operation
1 = TxFIFOmand Tx block are reset.
1 = RxFIFO and Rx block are reset.
1 = DMA Tx block is reset.
1 = DMA Rx block is reset.
1 = Tx enabled
[4] Tx enable (TxEN)
0 = Tx disabled
[5] Rx enable (RxEN)
0 = Rx disabled
1 = Rx enabled
[6] DMA Tx enable (DTxEN)
0 = DMA Tx disabled
1 = DMA Tx enabled
[7] DMA Rx enable (DRxEN)
0 = DMA Rx disabled
1 = DMA Rx enabled
[8] DPLL enable (DPLLEN)
0 = Disable
1 = Enable; DPLL enters search mode for a locking edge in the incoming data stream.
[9] BRG enable (BRGEN)
0 = BRG counter is inbibited.
1 = BRG counter is enabled.
[10] Tx 4 word burst mode (Tx4WD)
0 = 1-word mode selected.
1 = 4-word mode selected.
[11] Rx 4 word burst mode (Rx4WD)
0 = 1-word mode selected.
1 = 4-word mode selected.
[13:12] Rx widget algnment (RxWA)
00 = No invalid byte
01 = 1 invalid byte
10 = 2 invalid byte
11 = 3 invalid byte
[14] DMA Tx stop or skip (DTxSTSK)
0 = DMA Tx skips when DMA not owner bit is set.
1 = DMA Tx stops when DMA not owner bit is set.
[15] DMA Rx stop or skip (DRxSTSK)
0 = DMA Rx skips when DMA not owner bit is set.
1 = DMA Rx stops when DMA not owner bit is set.
[16] DMA Rx memory address decrement (DRxMADEC)
0 = Address is incremented.
1 = Address is decremented.
[17] Tx flag idle (TxFLAG)
0 = Enter mark idle mode (a bit pattern of consecutive ones)
1 = Enter time fill mode (a bit pattern of consecutive opening (closing) flag, as in string
01111110 01111110......
Figure 8-14. HDLC Control Register (HCON)
8-33