HDLC CONTROLLERS
S3C4510B
Table 8-9. HCON Register Description (Continued)
Bit Name Description
Bit
Number
[23]
Tx preamble (TxPRMB) When this bit is set to '1', the content of the HPRMB register is transmitted
as many TxPL bit values in interrupt mode instead of mark idle or time fill
mode. This is useful for sending the data needed by the DPLL to lock the
phase. In DMA mode, this bit is meaningless.
[24]
[25]
Tx data terminal ready
(TxDTR)
The TxDTR bit directly controls the nDTR output state. Setting this bit
forces the nDTR pin to Low level. When you clear the TxDTR bit, nDTR
goes High.
Rx frame discontinue
(RxDISCON)
When this bit is set, the frame currently received is ignored and the data in
this frame is discarded. Only the last frame received is affected. There is
no effect on subsequent frames, even if the next frame enters the receiver
when the discontinue bit is set. This bit is automatically cleared after a
cycle.
[26]
[27]
[28]
Tx no CRC (TxNOCRC) When this bit is set to '1', the CRC is not appended to the end of a frame
by hardware.
Rx no CRC (RxNOCRC) When this bit is set to '1', the receiver does not check for CRC by
hardware. (CRC data is always moved to the HRxFIFO.)
Auto enable (AutoEN)
This bit programs the function of both nDCD and nCTS. However, TxEN
and RxEN must be set before the nCTS and nDCD pins can be used.
When this bit is '0', if the nCTS becomes high, the transmitter sends mark
idle pattern. However, though the nDCD becomes high, the receiver can
receive the data.
When this bit is '1', if the nCTS becomes high, the transmitter send mark
idle but clears the HTxFIFO and the Tx block. If nDCD becomes high, the
receiver can't operate, and the HRxFIFO and Rx blocks are cleared.
[31:29] Reserved
Not applicable.
8-32
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