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S3C4510B 参数 Datasheet PDF下载

S3C4510B图片预览
型号: S3C4510B
PDF下载: 下载PDF文件 查看货源
内容描述: 三星S3C4510B的16位/ 32位RISC微控制器是一款高性价比,高性能的基于以太网的系统微控制器解决方案。 [Samsungs S3C4510B 16/32-bit RISC microcontroller is a cost-effective, high-performance microcontroller solution for Ethernet-based systems.]
分类和应用: 微控制器以太网
文件页数/大小: 422 页 / 2160 K
品牌: SAMSUNG [ SAMSUNG ]
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S3C4510B  
ETHERNET CONTROLLER  
RECEIVING A FRAME  
The receive block, when enabled, constantly monitors a data stream coming either from the MII or, if in loop-  
back mode, from the transmit block. The MII supplies from zero to seven bytes of preamble, followed by the start  
frame delimiter (SFD). The receive block checks that the first nibbles received are preamble, and then looks for  
the SFD (10101011) in the first eight bytes. If it does not detect the SFD by then, it treats the packet as a  
fragment and discards it.  
The first nibble of destination address follows the SFD, least-significant bits first. When it has received a byte,  
the receive block generates parity, stores the byte with its parity in the receive FIFO, and asserts Rx_rdy. It  
combines subsequent nibbles into bytes and stores them in the FIFO.  
BDI RECEIVE DATA TIMING  
When the system asserts Rx_rd#, the receive block reads the first byte from the FIFO, checks parity, and drives  
the byte on Rx_DB, and the byte's parity on Rx_par. If the FIFO is now empty, it drops Rx_rdy. When it drives  
out the last byte of a packet, it asserts Rx_EOF.  
Figure 7-19 shows the timing sequence for transmitting bytes back-to-back, transmitting with wait states, and  
transmitting the last byte.  
Sys_clk  
Rx_rdy  
Rx_rd#  
B1  
B2  
B3  
BN  
Rx_DB  
Rx_par  
PAR  
PAR  
PAR  
PAR  
Rx_EOF  
Figure 7-21. BDI Receive Data Timing  
7-55  
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