ETHERNET CONTROLLER
S3C4510B
RECEIVE FRAME TIMING WITH/WITHOUT ERROR
If, during frame reception, both Rx_DV and Rx_er are asserted, a CRC error is reported for the current packet.
As each nibble of the destination address is received, the CAM block attempts to recognize it. After receiving the
last destination address nibble, if the CAM block rejects the packet, the receive block asserts the Rx_toss signal,
and discards any bytes not yet removed from the receive FIFO that came from the current packet. If this
operation leaves the FIFO empty, it drops Rx_rdy.
Figure 7-20 shows the MII receive data timing without error. The RX_DV signal, which entered the MII from the
PCS layer, will be ON when the PCS layer recovers the Rx_clk from the receive bit stream and delivers the
nibble data on RxD[3:0] data line. The RX_DV signal must be ON before the starting frame delimiter(SFD) is
received. When the Rx_DV signal is ON, the preamble and SFD parts of the frame header are delivered to MII,
synchronized with the 25-MHz Rx_clk. (The carrier sense (CrS) signal was turned on during receive frame.)
As its response to the Rx_er signal, the MII immediately inserts an alternative data bit stream into the receive
data stream. As a result, the MAC discards this received error frame using the FCS.
Rx_clk
Rx_DV
Preamble
SFD
DA
SFD
RxD [3:0]
Crs
Rx_er
Figure 7-22. Receiving Frame without Error
Rx_clk
Rx_DV
Preamble
SFD
DA
SFD
RxD [3:0]
Crs
Rx_er
Figure 7-23. Receiving Frame with Error
7-56
SAMSUNG [ SAMSUNG ]
