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S3C4510B 参数 Datasheet PDF下载

S3C4510B图片预览
型号: S3C4510B
PDF下载: 下载PDF文件 查看货源
内容描述: 三星S3C4510B的16位/ 32位RISC微控制器是一款高性价比,高性能的基于以太网的系统微控制器解决方案。 [Samsungs S3C4510B 16/32-bit RISC microcontroller is a cost-effective, high-performance microcontroller solution for Ethernet-based systems.]
分类和应用: 微控制器以太网
文件页数/大小: 422 页 / 2160 K
品牌: SAMSUNG [ SAMSUNG ]
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ETHERNET CONTROLLER  
S3C4510B  
THE MII STATION MANAGER  
The MDIO (management data input/output) signal line is the transmit and receive path for control/status  
information for the station management entity, STA. The STA controls and reads the current operating status of  
the PHY layer. The speed of transmit and receive operations is determined by the management data clock,  
MDC.  
The frame structure of the STA which writes command to control registers, or which reads the status register of a  
PHY device, is shown Table 7-45. The PHY address is defined as the identification (ID) value of the various PHY  
devices that may be concected to a single MAC. Register addresses can contain the ID value for up to 32 types  
of PHY registers.  
Turn-around bits are used to regulate the turn-around time of the transmit/receive direction between the STA and  
a PHY device. So that the STA can read the set value of a PHY device register, it must transmit the frame data,  
up to a specific register address, to the PHY device. During the write time (which is an undirected transmission),  
the STA transmits a stream of turn-around bits. As a result, by transmitting a write or read message to a PHY  
device through the MDIO, the STA can issue a request to set the operation or to read the operation status.  
As its response this message, the PHY device resets itself, sets loop-back mode, selects active/non-active auto-  
negotiation process, separates the PHY and MII electrically, and determines whether or not to activate the  
collision detection process.  
When it receives a read command, the PHY reports the kind of PHY device it is, such as 100Base-T4, FDX  
100base-X, HDX 100Base-X, 10-Mb/s FDX, or 10-Mb/s HDX.  
Table 7-45. STA Frame Structure Description  
Preamble Start of Operation  
PHY  
Register Turnaround  
Data  
Idle  
Frame  
Code  
Address Address  
Write  
(Command)  
11111111  
(32 bits)  
01  
01 (write)  
5 bits  
5 bits  
5 bits  
5 bits  
10 (2 bits) 16 bits  
(register  
Z
value)  
Read (Status) 11111111  
(32 bits)  
01  
10 (read)  
Z0  
16 bits  
(register  
value)  
Z
Direction: STA to PHY  
Direction: PHY to STA  
7-58  
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