S3C4510B
ETHERNET CONTROLLER
MAC Receive Control Register
To issue an interrupt after each packet is received, set the enable good bit and all of the error enable bits in the
MACRXCON register. You can also enable interrupts for specific conditions. Standard packet length values do
not include a preamble or a start frame delimiter (SFD).
Table 7-26. MACRXCON Register
Registers
Offset
R/W
Description
Receive control
Reset Value
MACRXCON
0XA010
R/W
0x00000000
Table 7-27. MAC Receive Control Register Description
Bit Number
Bit Name
Description
[0]
Receive enable (RxEn)
Set this bit to "1" to enable MAC receive operation. If "0", stop
reception immediately.
[1]
[2]
Receive halt request (RxHalt)
Long enable (LongEn)
Set this bit to halt reception after completing the reception of
any current packet.
Set this bit to receive frames with lengths greater than 1518
bytes.
[3]
[4]
Short enable (ShortEn)
Set this bit to receive frames with lengths less than 64 bytes.
Strip CRC value (StripCRC)
Set this bit to check the CRC, and then strip it from the
message.
[5]
[6]
Pass control packet (PassCtl)
Set this bit to enable the passing of control packets to a MAC
client.
Ignore CRC value
(IgnoreCRC)
Set this bit to disable CRC value checking.
[7]
[8]
Reserved
Not applicable.
Enable alignment (EnAlign)
Set this bit to enable the alignment interrupt. An alignment
interrupt occurs when a packet is received whose length (in bits)
is not a multiple of eight, and whose CRC is invalid.
[9]
Enable CRC error
(EnCRCErr)
Set this bit to enable the CRC interrupt. A CRC interrupt occurs
when a packet is received whose CRC is invalid or if, during its
reception, the PHY asserts Rx_er.
[10]
[11]
Enable overflow (EnOver)
Enable long error (EnLongErr)
Reserved
Set this bit to enable the overflow interrupt. An overflow
interrupt is generated when a packet is received and the MAC
receive FIFO is full.
Set this bit to enable the long error interrupt. A long error
interrupt is generated when a frame longer than 1518 bytes is
received (unless the long enable bit is set).
[12]
[13]
Not applicable.
Enable receive parity
(EnRxPar)
Set this bit to enable a receive parity interrupt if the MAC
receive FIFO detects a parity error.
[14]
Enable Good (EnGood)
Set this bit to enable the good (packet) interrupt upon error-free
reception of a complete data packet.
[31:15]
Reserved
Not applicable.
NOTE: The frame lengths given above do not include preamble and start frame delimiter (SFD).
7-39
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