PRODUCT OVERVIEW
S3C4510B
SPECIAL REGISTERS
Table 1-5. S3C4510B Special Registers
R/W Description
Group
Registers
Offset
0x0000
0x3000
0x3008
0x300C
0x3010
0x3014
0x3018
0x301C
0x3020
0x3024
0x3028
0x302C
0x3030
0x3034
0x3038
0x303C
0x9000
0x9004
Reset/Value
0x37FFFF91
0x00000000
0x00000000
0x00000000
0x00000000
0x20000060
0x00000060
0x00000060
0x00000060
0x00000060
0x00000060
0x00000000
0x00000000
0x00000000
0x00000000
0x000083FD
0x00000000
0x00000000
System
SYSCFG
R/W System configuration register
Manager CLKCON
EXTACON0
EXTACON1
EXTDBWTH
ROMCON0
R/W Clock control register
R/W External I/O timing register 1
R/W External I/O timing register 2
R/W Data bus width for each memory bank
R/W ROM/SRAM/Flash bank 0 control register
R/W ROM/SRAM/Flash bank 1 control register
R/W ROM/SRAM/Flash bank 2 control register
R/W ROM/SRAM/Flash bank 3 control register
R/W ROM/SRAM/Flash bank 4 control register
R/W ROM/SRAM/Flash bank 5 control register
R/W DRAM bank 0 control register
ROMCON1
ROMCON2
ROMCON3
ROMCON4
ROMCON5
DRAMCON0
DRAMCON1
DRAMCON2
DRAMCON3
REFEXTCON
R/W DRAM bank 1 control register
R/W DRAM bank 2 control register
R/W DRAM bank 3 control register
R/W Refresh and external I/O control register
R/W Buffered DMA receive control register
R/W Buffered DMA transmit control register
Ethernet
(BDMA)
BDMATXCON
BDMARXCO
N
BDMATXPTR
BDMARXPTR
BDMARXLSZ
BDMASTAT
CAM
0x9008
0x900C
0x9010
0x9014
R/W Transmit frame descriptor start address
R/W Receive frame descriptor start address
R/W Receive frame maximum size
R/W Buffered DMA status
0x00000000
0x00000000
Undefined
0x00000000
Undefined
0x9100–
0x917C
W
CAM content (32 words)
BDMATXBUF
BDMARXBUF
0x9200–
0x92FC
R/W BDMA Tx buffer (64 words) for test mode
addressing
Undefined
Undefined
0x9800–
0x99FC
R/W BDMA Rx buffer (64 words) for test mode
addressing
1-22
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