PRODUCT OVERVIEW
S3C4510B
INSTRUCTION SET
The S3C4510B instruction set is divided into two subsets: a standard 32-bit ARM instruction set and a 16-bit
THUMB instruction set.
The 32-bit ARM instruction set is comprised of thirteen basic instruction types, which can, in turn, be divided into
four broad classes:
·
·
·
Four types of branch instructions which control program execution flow, instruction privilege levels, and
switching between an ARM code and a THUMB code.
Three types of data processing instructions which use the on-chip ALU, barrel shifter, and multiplier to
perform high-speed data operations in a bank of 31 registers (all with 32-bit register widths).
Three types of load and store instructions which control data transfer between memory locations and the
registers. One type is optimized for flexible addressing, another for rapid context switching, and the third for
swapping data.
·
Three types of co-processor instructions which are dedicated to controlling external co-processors. These
instructions extend the off-chip functionality of the instruction set in an open and uniform way.
NOTE
All 32-bit ARM instructions can be executed conditionally.
The 16-bit THUMB instruction set contains 36 instruction formats drawn from the standard 32-bit ARM instruction
set. The THUMB instructions can be divided into four functional groups:
·
·
·
·
Four branch instructions.
Twelve data processing instructions, which are a subset of the standard ARM data processing instructions.
Eight load and store register instructions.
Four load and store multiple instructions.
NOTE
Each 16-bit THUMB instruction has a corresponding 32-bit ARM instruction with an identical
processing model.
The 32-bit ARM instruction set and the 16-bit THUMB instruction set are good targets for compilers of many
different high-level languages. When an assembly code is required for critical code segments, the ARM
programming technique is straightforward, unlike that of some RISC processors which depend on sophisticated
compiler technology to manage complicated instruction interdependencies.
Pipelining is employed so that all parts of the processor and memory systems can operate continuously.
Typically, while one instruction is being executed, its successor is being decoded, and the third instruction is
being fetched from memory.
1-18
SAMSUNG [ SAMSUNG ]
