S3C4510B
PRODUCT OVERVIEW
EXCEPTIONS
An exception arises when the normal flow of program execution is interrupted, e.g., when processing is diverted
to handle an interrupt from a peripheral. The processor state just prior to handling the exception must be
preserved so that the program flow can be resumed when the exception routine is completed. Multiple exceptions
may arise simultaneously.
To process exceptions, the S3C4510B uses the banked core registers to save the current state. The old PC value
and the CPSR contents are copied into the appropriate R14 (LR) and SPSR registers. The PC and mode bits in
the CPSR are adjusted to the value corresponding to the type of exception being processed.
The S3C4510B core supports seven types of exceptions. Each exception has a fixed priority and a corresponding
privileged processor mode, as shown in Table 1-4.
Table 1-4. S3C4510B CPU Exceptions
Exception
Mode on Entry
Supervisor mode
Priority
Reset
1 (highest)
Data abort
Abort mode
2
FIQ
FIQ mode
3
IRQ
IRQ mode
4
Prefetch abort
Undefined instruction
SWI
Abort mode
5
6
Undefined mode
Supervisor mode
6 (lowest)
1-21
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