S3C4510B
PRODUCT OVERVIEW
MEMORY INTERFACE
The CPU memory interface has been designed to help the highest performance potential to be realized without
incurring high costs in the memory system. Speed-critical control signals are pipelined so that system control
functions can be implemented in standard low-power logic. These pipelined control signals allow you to fully
exploit the fast local access modes, offered by industry standard dynamic RAMs.
OPERATING STATES
From a programmer¢s point of view, the ARM7TDMI core is always in one of two operating states. These states,
which can be switched by software or by exception processing, are:
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ARM state (when executing 32-bit, word-aligned, ARM instructions), and
THUMB state (when executing 16-bit, half-word aligned THUMB instructions).
OPERATING MODES
The ARM7TDMI core supports seven operating modes:
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User mode: a normal program execution state
FIQ (Fast Interrupt Request) mode: for supporting a specific data transfer or channel processing
IRQ (Interrupt ReQuest) mode: for general purpose interrupt handling
Supervisor mode: a protected mode for the operating system
Abort mode: entered when a data or instruction pre-fetch is aborted
System mode: a privileged user mode for the operating system
Undefined mode: entered when an undefined instruction is executed
Operating mode changes can be controlled by software. They can also be caused by external interrupts or
exception processing. Most application programs execute in user mode. Privileged modes (that is, all modes
other than User mode) are entered to service interrupts or exceptions, or to access protected resources.
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