PRODUCT OVERVIEW
S3C4510B
REGISTERS
The S3C4510B CPU core has a total of 37 registers: 31 general-purpose 32-bit registers, and 6 status registers.
Not all of these registers are always available. Whether a registers is available to the programmer at any given
time depends on the current processor operating state and mode.
NOTE
When the S3C4510B is operating in ARM state, 16 general registers and one or two status registers can
be accessed at any time. In privileged mode, mode-specific banked registers are switched in.
Two register sets, or banks, can also be accessed, depending on the core¢s current state, the ARM state register
set and the THUMB state register set:
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The ARM state register set contains 16 directly accessible registers: R0-R15. All of these registers, except for
R15, are for general-purpose use, and can hold either data or address values. An additional (17th) register,
the CPSR (Current Program Status Register), is used to store status information.
·
The THUMB state register set is a subset of the ARM state set. You can access 8 general registers, R0-R7,
as well as the program counter (PC), a stack pointer register (SP), a link register (LR), and the CPSR. Each
privileged mode has a corresponding banked stack pointer, link register, and saved process status register
(SPSR).
The THUMB state registers are related to the ARM state registers as follows:
·
·
·
THUMB state R0-R7 registers and ARM state R0–R7 registers are identical
THUMB state CPSR and SPSRs and ARM state CPSR and SPSRs are identical
THUMB state SP, LR, and PC are mapped directly to ARM state registers R13, R14, and R15, respectively
In THUMB state, registers R8-R15 are not part of the standard register set. However, you can access them for
assembly language programming and use them for fast temporary storage, if necessary.
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