S3C4510B
PRODUCT OVERVIEW
Table 1-5. S3C4510B Special Registers (Continued)
Group
Ethernet
(MAC)
Registers
MACON
Offset
0xA000
0xA004
0xA008
0xA00C
0xA010
0xA014
0xA018
0xA01C
0xA028
0xA03C
0xA040
0xA044
0x9040
0x7000
0x7004
0x7008
0x700C
0x7010
0x7014
0x7018
0x701C
0x7020
0x7024
0x7028
0x702C
0x7030
0x7034
0x7038
0x703C
0x7040
0x7040
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Ethernet MAC control register
CAM control register
Reset/Value
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
CAMCON
MACTXCON
MACTXSTAT
MACRXCON
MACRXSTAT
STADATA
STACON
MAC transmit control register
MAC transmit status register
MAC receive control register
MAC receive status register
R/W Station management data
R/W Station management control and address
R/W CAM enable register
0x00006000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00010400
0x00000000
–
CAMEN
EMISSCNT
EPZCNT
R/W Missed error count register
R
R
R
Pause count register
ERMPZCNT
ETXSTAT
HMODE
Remote pause count register
Transmit control frame status
HDLC
R/W HDLC mode register
Channel A HCON
HSTAT
R/W HDLC control register
R/W HDLC status register
R/W HDLC interrupt enable register
HINTEN
HTXFIFOC
W
W
R
TxFIFO frame continue register
TxFIFO frame terminate register
HDLC RxFIFO entry register
HTXFIFOT
HRXFIFO
HBRGTC
HPRMB
–
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0xFFFFFFFF
0xFFFFFFFF
0xXXXX0000
0xXXXX0000
R/W HDLC baud rate generate time constant
R/W HDLC preamble constant
R/W HDLC station address 0
HSAR0
HSAR1
R/W HDLC station address 1
HSAR2
R/W HDLC station address 2
HSAR3
R/W HDLC station address 3
HMASK
R/W HDLC mask register
DMATxPTR
DMARxPTR
HMFLR
R/W DMA Tx buffer descriptor pointer
R/W DMA Rx buffer descriptor pointer
R/W Maximum frame length register
R/W DMA receive buffer size register
HRBSR
1-23
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