SYSTEM MANAGER
S3C4510B
EXTERNAL BUS MASTERSHIP
The S3C4510B can receive and acknowledge bus request signals (ExtMREQs) that are generated by an external
bus master. When the CPU asserts an external bus acknowledge signal (ExtMACK), mastership is granted to the
external bus master, assuming the external bus request is still active.
When the external bus acknowledge signal is active, the S3C4510B's memory interface signals go to high-
impedance state so that the external bus master can drive the required external memory interface signals.
The S3C4510B does not perform DRAM refreshes when it is not the bus master. When an external bus master is
in control of the external bus, and if it retains control for a long period of time, it must assume the responsibility of
performing the necessary DRAM refresh operations.
SCLK
MCLKO
tEMZ
Address, Data, nOE,
nWBE, nDWE, nRCS
, nCAS, nRAS
Data
Data
tEMRh
tEMRs
ExtMREQ
ExtMACK
tEMAr
tEMAf
Figure 4-5. External Bus Request Timing
NOTE: When External Bus Master requests the ExtMREQ during the Sync DRAM writing cycles, the ExtMACK can be
generated with the wrong writing control signals of Sync DRAM. Just floating the Sync DRAM control signals at the
time ExtMACK , it can cause the feasible active writing on the Sync DRAM. As the result, the wrong data can be
written into unexpected address on Sync DRAM. If this address is in the range of stack or code area, the crash will
be happen sooner or later. The other memory interfaces doesn’t have this problem, which is asynchronous with
MCLKO, that is why Sync DRAM write cycle only. You can avoid this by disabling the SDCS (Sync DRAM Chip
Select HIGH) as soon as receiving the ExtMACK and driving the Address and Data after one or two MCLKO cycles.
4-18
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