OneNAND512Mb(KFG1216U2B-xIB6)
3.3 Reset Mode Operation
FLASH MEMORY
The One NAND has 4 reset modes: Cold/Warm/Hot Reset, and NAND Flash Array Reset. Section 3.3 discusses the operation of
these reset modes.
The Register Reset Table shows the which registers are affected by the various types or Reset operations.
Internal Register Reset Table
Hot
Reset
(00F3h) (BP-F0h)
Hot
Reset
NAND Flash
Core Reset
(00F0h)
Warm Reset
(RP)
Internal Registers
Default Cold Reset
F000h Manufacturer ID Register (R)
00ECh
(Note 3)
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
F001h Device ID Register (R): OneNAND
F002h Version ID Register (R)
N/A
N/A
N/A
N/A
F003h Data Buffer size Register (R)
0800h
0200h
0201h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
40C0h
0000h
-
N/A
N/A
N/A
F004h Boot Buffer size Register (R)
N/A
N/A
N/A
F005h Amount of Buffers Register (R)
F006h Technology Register (R)
N/A
N/A
N/A
N/A
N/A
N/A
F100h Start Address1 Register (R/W): FBA
F101h Start Address2 Register (R/W): Reserved
F102h Start Address3 Register (R/W): FCBA
F103h Start Address4 Register (R/W): FCPA, FCSA
F104h Start Address5 Register (R/W): FPC
F107h Start Address8 Register (R/W): FPA, FSA
F200h Start Buffer Register (R/W): BSA, BSC
F220h Command Register (R/W)
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
40C0h
0000h
8080h
0000h
N/A
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
(Note1)
0000h
8010h
0000h
N/A
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
(Note1)
0000h
8010h
N/A
F221h System Configuration 1 Register (R/W)
F240h Controller Status Register (R)
F241h Interrupt Status Register (R/W)
F24Ch Start Block Address (R/W)
0000h
N/A
F24Dh End Block Address: N/A
N/A
F24Eh NAND Flash Write Protection Status (R)
FF00h ECC Status Register (R) (Note2)
FF01h ECC Result of Sector 0 Main area data Register(R)
0002h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0002h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0002h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
N/A
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
ECC Result of Sector 0 Spare area data Register (R)
ECC Result of Sector 1 Main area data Register(R)
FF02h
FF03h
FF04h ECC Result of Sector 1 Spare area data Register (R)
ECC Result of Sector 2 Main area data Register(R)
ECC Result of Sector 2 Spare area data Register (R)
FF05h
FF06h
FF07h ECC Result of Sector 3 Main area data Register(R)
ECC Result of Sector 3 Spare area data Register (R)
FF08h
NOTE: 1) RDYpol, INTpol, IOBE are reset by Cold reset. The other bits except OTP and OTP are reset by cold/warm/hot reset.
L
BL
2) ECC Status Register & ECC Result Registers are reset when any command is issued.
3) Refer to Device ID Register F001h.
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