OneNAND512Mb(KFG1216U2B-xIB6)
3.2 Device Bus Operation
FLASH MEMORY
The device bus operations are shown in the table below.
Operation
Standby
CE
H
OE
X
WE
X
ADD0~15 DQ0~15
RP
H
CLK
X
AVD
X
X
X
High-Z
High-Z
Data In
Warm Reset
X
X
X
L
X
X
Asynchronous Write
L
H
L
Add. In
H
L
X
Asynchronous Read
Load Initial Burst Read
Burst Read
L
L
L
L
H
L
H
H
H
Add. In
Add. In
X
Data Out
X
H
H
H
L
or L
Burst Data
Out
X
Terminate Burst Read
Cycle
H
X
X
X
H
X
X
X
High-Z
High-Z
H
L
X
X
X
X
Terminate Burst Read
Cycle via RP
Terminate Current Burst
Read Cycle and Start
New Burst Read Cycle
H
H
Add In
High-Z
H
Note : L=VIL (Low), H=VIH (High), X=Don’t Care.
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