K9W4G08U1M
K9K2G08Q0M
K9K2G08U0M
K9W4G16U1M
K9K2G16Q0M
K9K2G16U0M
FLASH MEMORY
BLOCK ERASE
The Erase operation is done on a block basis. Block address loading is accomplished in three cycles initiated by an Erase Setup com-
mand(60h). Only address A18 to A28(X8) or A17 to A27(X16) is valid while A12 to A17(X8) or A11 to A16(X16) is ignored. The Erase
Confirm command(D0h) following the block address loading initiates the internal erasing process. This two-step sequence of setup
followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions.
At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When
the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 13 details the sequence.
Figure 13. Block Erase Operation
tBERS
R/B
"0"
Pass
60h
I/O0
Fail
70h
Address Input(3Cycle)
I/Ox
D0h
"1"
Block Add. : A12 ~ A28 (X8)
or A11 ~ A27 (X16)
READ STATUS
The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether
the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs
the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows
the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE
does not need to be toggled for updated status. Refer to table 2 for specific Status Register definitions. The command register
remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read
cycle, the read command(00h) should be given before starting read cycles.
Table2. Read Staus Register Definition
I/O No.
I/O 0
Page Program
Pass/Fail
Block Erase
Pass/Fail
Not use
Cache Prorgam
Pass/Fail(N)
Pass/Fail(N-1)
Not use
Read
Not use
Definition
Pass : "0"
Fail : "1"
Fail : "1"
I/O 1
Not use
Not use
Pass : "0"
I/O 2
Not use
Not use
Not use
Don’t -cared
Don’t -cared
Don’t -cared
Busy : "0"
I/O 3
Not Use
Not Use
Not Use
Not Use
I/O 4
Not Use
Not Use
Not Use
Not Use
I/O 5
Ready/Busy
Ready/Busy
Write Protect
Ready/Busy
Ready/Busy
Write Protect
True Ready/Busy
Ready/Busy
Write Protect
Ready/Busy
Ready/Busy
Write Protect
Ready : "1"
Ready : "1"
I/O 6
Busy : "0"
I/O 7
Protected : "0"
Not Protected
I/O 8~15
(X16 device
only)
Not use
Not use
Not use
Not use
Don’t -care
NOTE : 1. True Ready/Busy represents internal program operation status which is being executed in cache program mode.
2. I/Os defined ’Not use’ are recommended to be masked out when Read Status is being executed.
35
SAMSUNG [ SAMSUNG ]
